In communication networks, high-speed digital receivers use analog-to-digital converters (ADCs) to convert a received signal into a digital form which allows a receiver to employ complex equalization logic. Usually, longer equalization is needed for higher signaling constellations and tougher channels. Thus, fast yet energy efficient ADCs are needed in high-speed digital receivers. A typical high-speed ADC resolution is between 5 to 8 bits.
ADCs with more than 6-bit precision running at several GHz are impractical to build as a single-channel ADC. Hence, typically, a number of slower ADCs are interleaved to overcome the speed limitation of a single-channel ADC. Successive-approximation-register (SAR) ADCs exhibit superior energy efficiency for medium-resolution applications.
Typically, a time-interleaved ADC uses a sampling and interleaving stage to receive and distribute input analog signals. More specifically, an input analog signal is demultiplexed by a first bank of switches, and sampled and held by another bank of switches. A sampled voltage is held on a storage capacitor at a designated point of time, and then buffered in a buffer circuit, for example, made of a source follower. The buffered voltage is supplied to a massive array of sub-ADCs through a set of output de-multiplexers. The N sub-ADCs are configured to perform analog-to-digital conversion in parallel, thereby offering N times higher conversion rates and input frequencies than if used non-interleaved.
However, due to the very large load capacitance from the succeeding ADC blocks, this type of signal chain has a major problem in that the buffer output is usually too slow to follow the high-speed input signal, leading to undesired Inter-Symbol Interference (ISI).
FIG. 1 illustrates the configuration of a buffer 100 in the sampling and interleaving stage of an individual channel in a time-interleaved ADC in accordance with the prior art. Diagram 160 shows the timing waveforms in various components in FIG. 1. The buffer circuit 100 may be used to buffer multiple sub-ADCs sequentially. The load of the buffer circuit 100 is collectively represented by the capacitor Chuge 120.
The input analog signal Vin is fed to a switch 140 which represents the combination of multiple demultiplexers and sampling and hold (S/H) switches. This switch 140 may be referred as a sampling switch herein. The switch 140 operates to select the buffer 100 and the associated sub-ADCs at a certain time window.
The buffer 100 is drawn at the transistor level using a PMOS source follower as an example. Only the half circuit is shown here. The same response problem applies to the NMOS version of the circuit. The full circuit is pseudo-differential with another copy that carries the inverted signal.
In time period as described herein, assuming that the buffer 100 starts with a settled condition, where all transients have died out and the sampling switch (SW) 140 is on. The source-to-gate voltage (Vsg) of the buffer 100 then assumes a certain value that follows from its bias current which is a positive value Vsg0. The parasitic capacitance at the gate node 112 of the transistor is represented as Ctiny 130. The drain node 111 is coupled to the ground and the source node 113 is coupled to a current source 115.
Assuming at the beginning of the nth cycle, the input voltage (Vin) transitions to a different level, e.g., is stepped down (as shown in the waveform 162), thus ΔV=Vin(n−1)−Vin(n) (positive number). The gate node voltage Vg at 112 can follow the variation of the input voltage (Vin) quickly (as shown in the waveform 164) because the capacitance Ctiny at this node is very small. In contrast, the source node voltage Vs (as shown in the waveform 163) follows very slowly due to the large load capacitance (Chuge) of the connected ADC bank and the interconnect network (not explicitly shown). For simplicity, the diagram 163 approximates Vs as staying constant during the initial transient, though it moves at some slow rate in reality. The net effect is that Vs−Vg becomes larger than Vsg0 after the applied step.
Next, the switch 140 (SW) turns off and the buffer 100 takes some time to settle. When settling is complete, Vsg returns to the same steadystate value Vsg0 that it started out with, e.g., by drawing additional charge to Csg 114. On the source side, this charge is readily available, since this node is resistive. However, at the gate side, the charge can only come via charge conservation from the node's parasitic capacitance Ctiny 130. Hence the gate node voltage Vs gets pulled down by an amount equal to ISI=ΔV·Csg/Ctiny=ΔV·k. In the discrete time domain, the buffer output voltage Vs(n) is represented as:Vs(n)=Vin(n)+Vsg0−ISI  (Equation 1)Vs(n)=Vin(n)+Vsg0−k(Vin(n−1)−Vin(n))  (Equation 2)Vs(n)=Vin(n)(1+k)−kVin(n−1)+Vsg0  (Equation 3)As shown in the Equations 1-3, the buffer output voltage Vs(n) is a function of Vin(n−1), meaning that the output signal has ISI.
FIG. 2 illustrates sample data plots of ADC frequency responses obtained by using the buffer shown in FIG. 1. The curve 210 shows the frequency response caused by the negative ISI term kVin (n−1). The curve 220 shows the finite acquisition bandwidth of the ADC front-end. The curve 230 shows the overall ADC frequency response which combines the ISI and the finite acquisition bandwidth. This response is undesired because it would take extra digital system resources to equalize it.
FIG. 3 illustrates the configuration of a buffer 300 in the sampling and interleaving stage in a time-interleaved ADC where the buffer 300 is capable of outputting a signal without ISI in accordance with the prior art. Compared with the buffer 100 shown in FIG. 3, the buffer 300 additionally includes a switch SWO 350 operable to isolate the large load capacitance Chuge while the input V1 is supplied. In this configuration, the turning-on of SWO 350 and the initial condition of Chuge 320 have no effect on the final output value Vs as long as the circuit is given enough time to settle. Thus both the gate Vg and source voltages Vs can follow quickly, and the analyzed ISI effect no longer occurs due to charge conservation at the gate node of the transistor, which defines the settling value. In this configuration, the buffer output voltage can be expressed asVs(n)=Vin(n)Vsg0  (Equation 4)Thus, the gain from the gate to the source is nearly unity. FIG. 4 shows the sample data plot of frequency response of the ADC as a result of using a buffer circuit configured as in FIG. 3. The data plot shows that the ISI effect is removed from the frequency response.